A Korean research team has developed a next-generation 3D memory technology that can process large volumes of data faster and with less power. The advance is expected to be used in building high-performance, low-power AI chips.
According to the science and technology community on the 21st, a research team led by Professor Kwon Ji-min of the School of Electrical Engineering at the Korea Advanced Institute of Science and Technology (KAIST) developed a multilayer interlayer insulation structure that improves the performance and stability of oxide vertical channel transistors (VCTs), a next-generation memory device. The work was carried out jointly with domestic researchers from UNIST, Yonsei University and others.
A VCT is a device in which the "channel," the path through which current flows in a semiconductor, is arranged vertically rather than horizontally, allowing chips to be stacked upward. Because it can place more devices in a smaller area than conventional planar semiconductors, it has drawn attention as a next-generation high-density memory technology. In particular, using an oxide semiconductor as the channel material can reduce leakage current and improve power efficiency.
The challenge was the stability of oxide semiconductors. When an "oxygen vacancy," an empty spot left when an oxygen atom is missing from within the oxide, occurs, the electrical properties of the device can become unstable. Conversely, supplying too much oxygen oxidizes the metal electrode, degrading performance.
In response, the team developed a multilayer insulation film composed of silicon nitride, silicon dioxide and silicon nitride (SiN/SiO₂/SiN). The core is a so-called "oxygen tunnel" structure that selectively controls the path of oxygen movement. It guides oxygen to move toward the oxide semiconductor to reduce oxygen vacancies, while preventing it from moving toward the metal electrode to suppress electrode oxidation.
As a result, the team achieved world-class current characteristics and data retention time in an oxide VCT. In particular, it confirmed high stability, with the threshold voltage — the level at which a transistor turns on — changing by 50 millivolts (mV) or less even after being operated repeatedly more than 10 million times.
The team also verified system-level performance by combining conventional silicon (Si)-based CMOS semiconductors with oxide semiconductors. If the technology is applied to compute-in-memory (CIM), which combines memory and computing functions in one place, it is expected to help reduce the amount of data movement in AI chips.
"Just as it is important to build a tall building stably to make it high, the key for a 3D semiconductor is to make it operate stably while stacking many devices," Professor Kwon said. "We expect this technology to accelerate the development of next-generation memory chips that raise AI computing speed while cutting power consumption."
The research results, recognized for their excellence, were published in the international journal Advanced Functional Materials on May 20 and were selected as a cover paper.
