Taiwan's TSMC, the world's largest semiconductor foundry, has successfully developed a chip built on a 1.6-nanometer process. Mass production, slated for the fourth quarter, is expected to proceed smoothly.
Taiwanese media including the Liberty Times and the Economic Daily News reported on the 20th, citing sources, that TSMC had "successfully developed and completed verification of A16 (1.6 nanometers), which adopts Super Power Rail (SPR), the industry's leading backside power delivery network (BSPDN) technology." TSMC had repeatedly stated its plan to develop the A16 technology within this year and begin mass production in the fourth quarter, and this marks the official completion of final development and verification.
The "A" in A16 stands for angstrom (Å), a unit representing one ten-billionth of a meter. Against this backdrop, ultra-fine processes below 2 nanometers, measured in fractions, are called "angstrom-class." TSMC's A16 is distinguished by using SPR technology to separate the power delivery network onto the backside of the wafer rather than the conventional front side. This eliminates the bottleneck between the signal wiring that carries data and the power wiring, maximizing power efficiency and performance. Compared with TSMC's N2P process, a refined version of its 2-nanometer node, the A16 is said to be 8 to 10% faster, consume 15 to 20% less power, and offer 8 to 10% greater chip density.
The A16 is a chip suited for artificial intelligence (AI) and high-performance computing (HPC), and is scheduled for mass production starting in the fourth quarter of this year. Furthermore, the successful development of the A16 process technology, an intermediate step toward the next-generation advanced silicon technology A14 (1.4 nanometers), is expected to keep the A14 mass production plan for 2028 on track. Mass production of the A13 and A12 is scheduled for 2029. Earlier, TSMC's board approved a capital expenditure plan of $29.4425 billion (about 41 trillion won) for advanced processes and packaging on the 11th.
On this successful A16 development, Taiwan's Economic Daily News assessed that "TSMC has maintained its technology gap with Samsung Electronics." In a 2022 announcement, Samsung Electronics said it would begin mass production of its 2-nanometer process in 2025 and its 1.4-nanometer process in 2027. However, Samsung Foundry revised its technology roadmap at the SAFE Forum 2026, pushing back mass production of its 1.4-nanometer process to 2029.
The industry views Samsung Electronics as currently prioritizing improved yields, higher output and expanded performance for its 2-nanometer process. With AI chips, including Nvidia products, preparing to shift from 3 nanometers to 2 nanometers, analysts say focusing on optimizing the 2-nanometer process to secure high-value orders is a wiser strategy.
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Meanwhile, Taiwanese media, citing sources, reported that a shortage in the production capacity of TSMC's advanced packaging technology, chip-on-wafer-on-substrate (CoWoS), had prompted some packaging orders to be transferred to Intel's Malaysia plant as a form of cooperation.
CoWoS is a technology that boosts data transfer speeds by horizontally placing a graphics processing unit (GPU) or logic chip (non-memory semiconductors that handle computation and logic) close to high-bandwidth memory (HBM) on a single substrate, and it is essential for manufacturing AI accelerator chips. A shortage in AI accelerator chip production via TSMC's CoWoS has been cited as a bottleneck for years.
On this, Liu Pei-chen, a researcher at the Taiwan Institute of Economic Research (TIER), predicted that as the entire industrial chain gradually moves toward mutual complementarity through more advanced specialization and regionalization, it will move away from the winner-take-all of the past and advance together to expand the AI market.
One expert forecast that "the surge in AI demand shows semiconductor-related companies gradually shifting from the past scramble for orders to a new phase of competing while also cooperating," adding that "a new division of labor, in which TSMC takes charge of advanced processes and other companies handle back-end packaging, appears likely to disperse geopolitical risk."
