Samsung Electronics (005930.KS) has identified optimized placement of logic and memory as its key move to break through the limits of next-generation artificial intelligence memory chips. The strategy aims to shift the paradigm of three-dimensional memory through structural innovation that fundamentally reduces data processing latency, moving beyond the physical stacking race of piling chips ever higher.
Choi Jang-suk, vice president and head of the product planning team at Samsung Electronics' memory business division, delivered a keynote address at the Memory Executive Summit of SEMICON Taiwan 2026 in Taipei on the 1st, where he presented the company's next-generation technology vision under the name CUBE, according to industry sources. CUBE is a development methodology for next-generation memory that takes its name from four elements: capacity, utilization, bandwidth and efficiency in power and heat.
Innovation in utilization drew the most emphasis in the presentation. "The core of 3D memory is not simply stacking chips but how each layer is utilized," Choi said in his keynote. "Samsung Electronics is focusing on optimizing the placement of logic and memory to eliminate data processing latency."
The remarks are read as a plan to tear down the persistent memory wall by optimizing the physical and structural placement of the two chips, at a time when surging AI computing loads are worsening data bottlenecks between processing units, or logic, and storage devices, or memory. Samsung also laid out the details of CUBE, including vertical expansion that does not increase printed circuit board area, improved bandwidth through shorter distances between dies, and minimized energy required to move a single bit of data.
Samsung Electronics is translating this technology vision into a concrete product roadmap. The company is developing HBM5, an eighth-generation high-bandwidth memory with twice the performance of the seventh-generation HBM4E, and plans to introduce zHBM, which will raise performance up to eightfold over HBM4E while cutting thermal resistance by up to 90%. It is also preparing zNAND-O, a hybrid solution tailored for large language models that overcomes the limits of both conventional DRAM and NAND, with sampling targeted for 2028.
Underpinning that leadership in advanced technology is market dominance and manufacturing competitiveness that outpace rivals. Samsung Electronics led the global DRAM market with a 39% share in the second quarter of this year, according to Counterpoint Research, well ahead of second-place SK hynix at 26% and third-place Micron at 25%. In the second-quarter NAND market tallied by TrendForce, Samsung also held the top spot with revenue of $23.06 billion and a 29.3% share.
The gap in production scale is even wider. Samsung Electronics' annual DRAM production capacity this year is estimated at 8.175 million 300-millimeter wafers, according to Omdia, compared with about 6.66 million for SK hynix and about 3.6 million for Micron. In NAND, Samsung is projected to produce 4.77 million wafers a year, far ahead of the combined 2.79 million or so from SK hynix and Solidigm.
