Samsung Electronics is accelerating production preparations for HBM5, its next-generation memory product set to launch after next year, while showcasing its related technological capabilities in high-bandwidth memory (HBM).
"HBM5 is expected to require an improvement in operating speed of about 50 percent or more over HBM4E," Koo Ja-heum, vice president of the technology development office at Samsung Electronics' (005930.KS) foundry business division, said on the 27th. "We plan to apply a 2-nanometer (nm) process using a gate-all-around (GAA) structure to the base die, and to implement through-silicon vias (TSV) with higher integration density."
The remarks signaled that Samsung Electronics has entered production preparations by preemptively specifying performance targets and process adoption plans for HBM5, expected to launch in 2028, following HBM4 this year and HBM4E next year. If Koo's statement is carried out, HBM5 will be the first HBM to apply a 2nm process to the base die. It can further enhance operating speed, bandwidth, and heat control performance compared with HBM4E, which uses a 4nm process. The base die is the bottommost layer of the HBM and serves to smoothly connect the DRAM and graphics processing unit (GPU) in the upper layers.
Koo said that Samsung Electronics is building advanced foundry expertise centered on the 2nm process by actively winning orders not only for HBM but also for Big Tech's artificial intelligence (AI) chip production. "We proved our process competitiveness last year by winning an order for Tesla's automotive 2nm product," he said. "From that starting point, orders have continued from a number of large customers including AI, high-performance computing (HPC), and cloud service providers (CSP)."
